The invention relates generally to testing of integrated circuits, and more particularly to methods, circuits and systems for applying voltage screening to integrated circuits containing memory arrays.
Consumer electronic devices and computers are on the path of ever-advancing power. Contributing to that advance is the ever-increasing performance of semiconductor memories. For example, semiconductor memories are becoming faster and more dense.
Development of faster and denser memories has generally involved advances both in semiconductor manufacturing technology and in memory circuit design. Advances in semiconductor manufacturing technology have included reduction of on-chip geometries and use of multiple levels of low resistance metal interconnect. Advances in circuit design have included use of sense amplifiers coupled to memory bitlines, as well as use of bitline equalizers to balance bitlines prior to read access.
While fast, high-density memories are desirable, it is at least equally desirable that semiconductor memories be reliable. Reliability issues, however, tend to become more difficult to resolve as the circuits become more complex. In the case of random access memory (RAM), the technology trend is to increasingly complex physical geometries and circuit architectures, particularly in combination with enhanced operating speeds and reduced voltages, and all leading to smaller design tolerances, lower signal margins, and other reliability issues not encountered by previous generations of memory circuits. And in the specific case of static RAM, reliability issues can develop over time, the issues being founded on defects which may be disguised, e.g., disguised by the positive feedback within the memory cell. Reliability issues, accordingly, have become a powerful force for development of testing solutions.
In addition to reliability, another important aspect of manufacturing successfully semiconductor memories is cost. The manufacture of semiconductor memory is carried on throughout the world and is very competitive, particularly on cost. Investment in the building, equipping and operating of the modern semiconductor manufacturing facility tends to drive unit costs higher. Notwithstanding such investment, unit costs are generally controlled by high volume, batch production. This production cost benefits, however, can be undermined if the memory device requires substantial time for proper testing, which problem tends to become ever acute as memories' advance in density and complexity.
The testing of semiconductor memories typically takes place prior to shipping the devices to customers and then, increasingly, through the customers' incorporation of the devices in their products and on through the use of such products in the field. Prior to shipping, the testing generally is performed in two phases. The first phase is typically referred to as "wafer probe" or "wafer sort". This phase includes the testing of functional and/or parametric performance of the devices as individual integrated circuits, typically while the integrated circuits are still in wafer form, i.e., before any tested integrated circuit has been cut apart from the wafer and while any special test pads are accessible. The second phase is typically referred to as "final test". This phase includes the testing of functional and/or parametric performance of the memory devices as individually packaged integrated circuits using external pins of the device.
Certain functional and parametric testing is difficult to implement in a cost effective manner. In wafer sort, for example, because the tested integrated circuit is in wafer form, it tends not to reach the same temperatures that a packaged integrated circuit reaches, particularly after a period of operation. Unfortunately, even at final sort the packaged integrated circuit takes additional time, under power, to reach the internal temperatures typically associated with marginal or failing performance. Any such additional time is recognized generally to increase the cost of testing.
One conventional solution to this problem has been to raise the integrated circuit's temperature through controlled application of heat (typically referred to as "heat soaking"). Even so, heat soaking relies on expensive equipment and yet can waste valuable time. As an example, heat soaking consumes time in ramping to each of the generally plural temperatures deemed necessary for proper testing.
Accordingly, a need exists for methods, apparatus and systems for cost-effectively screening semiconductor products, such as memories, for reliability problems.